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| powerpc 740 and powerpc 750 microprocessor datasheet cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 version 1.02 12/8/99 ibm microelectronics division
notices before using this information and the product it supports, be sure to read the general information on the back cover of this book. trademarks the following are trademarks of international business machines corporation in the united states, or other countries, or both: ibm ibm logo powerpc aix powerpc 750 powerpc 740 other company, product, and service names may be trademarks or service marks of others. this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product without notice. ? international business machines corporation 1999. portions hereof ?international business machines corporation, 1991-1999. all rights reserved. 12/8/99 version 1.02 page 3 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 table of contents preface ........................................................................................................................ ............................. 4 new features for dd3.x ......................................................................................................... ................... 4 overview ....................................................................................................................... ............................ 5 features ....................................................................................................................... ............................ 6 general parameters ............................................................................................................. .................... 8 electrical and thermal characteristics ......................................................................................... ............ 9 dc electrical characteristics .................................................................................................. .............. 9 ac electrical characteristics .................................................................................................. ................ 13 clock ac specifications ........................................................................................................ .............. 13 60x bus input ac specifications ................................................................................................ ......... 14 60x bus output ac specifications ............................................................................................... ....... 16 l2 clock ac specifications ..................................................................................................... ............ 18 l2 bus input ac specifications ................................................................................................. .......... 20 l2 bus output ac specifications ................................................................................................ ........ 21 ieee 1149.1 ac timing specifications ........................................................................................... ....... 22 powerpc 740 microprocessor pin assignments .................................................................................... 2 4 powerpc 740 microprocessor pinout listings ..................................................................................... .. 25 powerpc 740 package ............................................................................................................ .............. 28 mechanical dimensions of the powerpc 740 255 cbga package .................................................... 29 powerpc 750 microprocessor pin assignments .................................................................................... 3 0 powerpc 750 package ............................................................................................................ .............. 33 mechanical dimensions of the powerpc 750 360 cbga package .................................................... 34 system design information ...................................................................................................... .............. 36 pll configuration .............................................................................................................. ................. 36 pll power supply filtering ..................................................................................................... ............ 37 decoupling recommendations ..................................................................................................... ...... 37 connection recommendations ..................................................................................................... ...... 37 output buffer dc impedance ..................................................................................................... ......... 38 pull-up resistor requirements .................................................................................................. ......... 39 thermal management information ................................................................................................. ..... 40 internal package conduction resistance ......................................................................................... .. 41 heat sink selection example .................................................................................................... .......... 44 ordering information ........................................................................................................... .................... 46 page 4 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 preface the powerpc 740 and powerpc 750 are members of the powerpc family of reduced instruction set com- puter (risc) microprocessors. the ppc740l and ppc750l microprocessors are the pid-8p implementa- tions of the powerpc 740 and powerpc 750 in ibm cmos 7s 0.20 m m copper technology. they are referred to in the body of this document as 740 and 750. information in this document does not apply to implementations of the powerpc 740 and powerpc 750 in other technologies, such as the pid-8t. the information in this document is also specific to revision level dd3.2 of the (pid-8p) ppc740l and ppc750l, and does not apply to previous revisions. this document is generally written in terms of the 750. unless otherwise noted, information that applies to the 750 also applies to the 740. exceptions are detailed. the 740 die is identical to the 750 die, but the 740 pack- age and pinout are different, in that the 740 does not pin out the l2 interface. the 740 uses the same die as the 750, but the 740 does not pin out the l2 cache interface. new features for dd3.x ? selectable i/o voltages on 60x bus and l2 bus. see table , recommended operating conditions, on page 9. older revs must leave these pins no connect or tied high for 3.3v i/os. ac timings are the same for all i/o voltages modes unless otherwise noted. ? 60x bus to core frequency now also supports the 10x ratio. see table , pll con?guration, on page 36. ? extra output hold on the 60x bus by l2_tstclk pin tied low is no longer available. the l2_tstclk pin must now be tied to ov dd for normal operation. see table , 60x bus output ac timing speci?cations for the 750 1 , on page 16. 12/8/99 version 1.02 page 5 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 overview the 750 is targeted for high performance, low power systems and supports the following power management features: doze, nap, sleep, and dynamic power management. the 750 consists of a processor core and an internal l2 tag combined with a dedicated l2 cache interface and a 60x bus. the l2 cache is not available with the 740. figure 1 shows a block diagram of the 750. figure 1. 750 block diagram fxu2 gprs lsu fpu instruction fetch system completion rename buffers unit 32k icache 32k dcache bht / biu biu 60x l2 cache fxu1 l2 tags dispatch branch unit btic control unit fprs rename buffers page 6 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 features this section summarizes features of the implementation of the powerpc 750 architecture. for details, see the powerpc 740 and powerpc750 users manual . ? branch processing unit - four instructions fetched per clock. - one branch processed per cycle (plus resolving 2 speculations). - up to 1 speculative stream in execution, 1 additional speculative stream in fetch. - 512-entry branch history table (bht) for dynamic prediction. - 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots. ? dispatch unit - full hardware detection of dependencies (resolved in the execution units). - dispatch two instructions to six independent units (system, branch, load/store, ?xed-point unit 1, ?xed-point unit 2, or ?oating-point). - serialization control (predispatch, postdispatch, execution, serialization). ? decode - register ?le access. - forwarding control. - partial instruction decode. ? load/store unit - one cycle load or store cache access (byte, half word, word, double word). - effective address generation. - hits under misses (one outstanding miss). - single-cycle misaligned access within double word boundary. - alignment, zero padding, sign extend for integer register ?le. - floating-point internal format conversion (alignment, normalization). - sequencing for load/store multiples and string operations. - store gathering. - cache and tlb instructions. - big and little-endian byte addressing supported. - misaligned little-endian support in hardware. ? fixed-point units - fixed-point unit 1 (fxu1); multiply, divide, shift, rotate, arithmetic, logical. - fixed-point unit 2 (fxu2); shift, rotate, arithmetic, logical. - single-cycle arithmetic, shift, rotate, logical. - multiply and divide support (multi-cycle). - early out multiply. ? floating-point unit - support for ieee-754 standard single- and double-precision ?oating-point arithmetic. - 3 cycle latency, 1 cycle throughput, single-precision multiply-add. - 3 cycle latency, 1 cycle throughput, double-precision add. - 4 cycle latency, 2 cycle throughput, double-precision multiply-add. - hardware support for divide. - hardware support for denormalized numbers. - time deterministic non-ieee mode. 12/8/99 version 1.02 page 7 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 ? system unit - executes cr logical instructions and miscellaneous system instructions. - special register transfer instructions. ? cache structure - 32k, 32-byte line, 8-way set associative instruction cache. - 32k, 32-byte line, 8-way set associative data cache. - single-cycle cache access. - pseudo-lru replacement. - copy-back or write-through data cache (on a page per page basis). - supports all powerpc memory coherency modes. - non-blocking instruction and data cache (one outstanding miss under hits). - no snooping of instruction cache. ? memory management unit - 128 entry, 2-way set associative instruction tlb. - 128 entry, 2-way set associative data tlb. - hardware reload for tlb's. - 4 instruction bat's and 4 data bats. - virtual memory support for up to 4 exabytes (2 52 ) virtual memory. - real memory support for up to 4 gigabytes (2 32 ) of physical memory. ? level 2 (l2) cache interface (not available on the 740) - internal l2 cache controller and 4k-entry tags; external data srams. - 256k, 512k, and 1 mbyte 2-way set associative l2 cache support. - copy-back or write-through data cache (on a page basis, or for all l2). - 64-byte (256k/512k) and 128-byte (l-mbyte) sectored line size. - supports ?ow-through (reg-buf) synchronous burst srams, pipelined (reg-reg) synchronous burst srams, and pipelined (reg-reg) late-write synchronous burst srams with optional parity checking. - supports core-to-l2 frequency divisors of ? 1, ? 1.5, ? 2, ? 2.5, and ? 3. the 750 supports the l2 fre- quency range speci?ed in section l2 clock ac speci?cations, on page 18. for higher l2 frequen- cies, please contact ppcsupp@us.ibm.com. ? bus interface - compatible with 60x processor interface. - 32-bit address bus with optional parity checking. - 64-bit data bus (can be operated in 32-bit data bus mode) with optional parity checking. - bus-to-core frequency multipliers from 2x to 10x. see the table , pll con?guration, on page 36. ? integrated power management - low-power 2.0/3.3v design. - three static power saving modes: doze, nap, and sleep. - automatic dynamic power reduction when internal functional units are idle. ? integrated thermal management assist unit - on-chip thermal sensor and control logic. - thermal management interrupts for software regulation of junction temperature. ? testability - jtag interface. page 8 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 general parameters the following list provides a summary of the general parameters of the 750. technology 0.20 m m cmos (general lithography), six-layer copper metallization 0.12 0.04 m m l eff die size 5.14mm x 7.78mm (40mm 2 ) transistor count 6.35 million logic design fully-static package 740: surface mount 21x21mm, 255-lead ceramic ball grid array (cbga) 750: surface mount 25x25mm, 360-lead ceramic ball grid array (cbga) ppc 740/ppc 750 core power supply 2v nominal (see application conditions) i/o power supply 3.3v 2.5v, or 1.8v nominal selectable) 12/8/99 version 1.02 page 9 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 electrical and thermal characteristics dc electrical characteristics the 750 60x bus power supply can be either 3.3v, 2.5v, or 1.8v nominal; likewise, the l2 power supply can be either 3.3v, 2.5v, or 1.8v nominal. see the pinout listing for more information absolute maximum ratings see notes characteristic symbol value unit core supply voltage v dd -0.3 to 2.5 v pll supply voltage av dd -0.3 to 2.5 v l2 dll supply voltage l2av dd -0.3 to 2.5 v 60x bus supply voltage ov dd(3.3v) -0.3 to 3.6 v ov dd(2.5v) -0.3 to 2.8 ov dd(1.8v) -0.3 to 2.1 l2 bus supply voltage l2ov dd -0.3 to 3.6 v input voltage v in(3.3v) -0.3 to 3.6 v v in(2.5v) -0.3 to 2.8 v in(1.8v) -0.3 to 2.1 storage temperature range t stg -55 to 150 c note: 1. functional and tested operating conditions are given in table recommended operating conditions, below. absolute maximum rat ings are stress rat- ings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliabili ty or cause permanent damage to the device. 2. caution: v in must not exceed ov dd by more than 0.3v at any time, including during power-on reset. this is a dc specification only. v in overshoot tran- sients up to ov dd +1v, and undershoots down to gnd-1v (both measured with the 740 in the circuit) are allowed for up to 5ns. 3. caution: ov dd must not exceed v dd /av dd by more than 2.0v at any time during normal operation. on power up and power down, ov dd is allowed to exceed v dd /av dd by up to 3.3v for up to 20 ms, or by up to 2.5v for 40 ms. excursions beyond 40 ms or 3.3v are not allowed. 4. caution: v dd /av dd must not exceed ov dd by more than 0.4v during normal operation. on power up and power down, v dd /av dd is allowed to exceed ov dd by up to1.0v for up to 20 ms, or by up to 0.7v for 40 ms. excursions beyond 40 ms or 1.0v are not allowed. recommended operating conditions characteristic symbol value unit notes core supply voltage v dd 2.0 v 1, 2 pll supply voltage av dd v dd v1 l2dll supply voltage l2av dd v dd v1 60x bus supply voltage, pin w1 tied high ov dd(3.3v) 3.135 to 3.465 v 1 60x bus supply voltage pin w1 tied to hreset ov dd(2.5v) 2.375 to 2.625 v 1 60x bus supply voltage, pin w1 tied to gnd ov dd(1.8v) 1.71 to 1.89 v 1 l2 bus supply voltage, pin a19 tied high l2ov dd(3.3v) 3.135 to 3.465 v 1 l2 bus supply voltage, pin a19 tied to hreset l2ov dd(2.5v) 2.375 to 2.625 v 1 note: 1. these are recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. v dd and t j are specified by the application conditions designator in the part number. see the part number key on page 43 for more informa tion. page 10 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 the 750 incorporates a thermal management assist unit (tau) composed of a thermal sensor, digital-to-ana- log converter, comparator, control logic, and dedicated special-purpose registers (sprs). see the powerpc 740 and powerpc 750 users manual for more information on the use of this feature. specifications for the thermal sensor portion of the tau are found in the table below. . l2 bus supply voltage, pin a19 tied to gnd l2ov dd(1.8v) 1.71 to 1.89 v 1 input voltage (under ac conditions, inputs must go rail-to- rail for maximum ac timing performance.) v in(60x) gnd to ov dd v1 v in(l2) gnd to l2ov dd v1 die-junction temperature t j -40 to 105 c 1, 2 package thermal characteristics 1 characteristic symbol 740 750 unit thermal resistance, junction-to-case (top sur- face of die) typical q jc 0.03 0.03 c/w thermal resistance, junction-to-balls, typical q jb 3.8 - 7.1 2 3.8 - 7.6 2 c/w thermal resistance, junction-to-ambient, at air- flow, no heat sink, typical 50 fpm 16.0 15.1 c/w 100 fpm 15.4 16.4 c/w 150 fpm 14.9 14.2 c/w 200 fpm 14.4 13.7 c/w package size 21 x 21 25 x 25 mm 2 die size 5.12 x 7.78 5.12 x 7.78 mm 2 note: 1. refer to section thermal management information, on page 40 for more information about thermal management. 2. 3.8 c/w is theoretical q jb mounted to infinite heat sink. the larger number applies to module mounted to a 1.8 mm thick, 2p card using 1 oz. copper power/gnd planes, with effective area for heat transfer of 75mm x 75mm. thermal sensor speci?cations see table recommended operating conditions, on page 9, for operating conditions. num characteristic minimum maximum unit notes 1 temperature range 0 128 c1 2 comparator settling time 20 ms 2 note: 1. the temperature is the junction temperature of the die. the thermal assist unit's (tau) raw output does not indicate an absol ute temperature, but it must be interpreted by software to derive the absolute junction temperature. for information on how to use and calibrate the ta u, contact ppcsupp@us.ibm.com. this specification reflects the temperature span supported by the design. 2. the comparator settling time value must be converted into the number of cpu clocks that need to be written into the thrm3 spr . for parts with nominal operating frequencies (speed sort) above 266 mhz, the settling time = 20 m s (266/nominal frequency). for example: for 500 mhz parts, settling time = 20 m s (266/500) = 10.6 m s. it is recommended that the maximum value be set in thrm3 under all conditions. 3. this value is guaranteed by design and is not tested. recommended operating conditions characteristic symbol value unit notes note: 1. these are recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. v dd and t j are specified by the application conditions designator in the part number. see the part number key on page 43 for more informa tion. 12/8/99 version 1.02 page 11 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 3 resolution 4 c3 4 drift, all sources .25 lsb 5 linearity, error over range 1 lsb 6 offset error, reducible 2 lsb dc electrical speci?cations see section recommended operating conditions, on page 9, for operating conditions. characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih(3.3v) 2.0 3.465 v 1,2 v ih(2.5v) 1.75 2.625 v ih()1.8v 1.4 1.89 input low voltage (all inputs except sysclk) v il(3.3v) gnd 0.8 v v il(2.5v) gnd 0.7 v il()1.8v gnd 0.5 sysclk input high voltage cv ih(3.3v) 2.0 3.465 v 1, 4 cv ih(2.5v) 2.0 2.625 cv ih(1.8v) 1.5 1.89 sysclk input low voltage cv il C 0.4 v 4 input leakage current, v in = ov dd i in C20 m a 1,2 hi-z (off state) leakage current, vin = ov dd i tsi C20 m a 1,2 output high voltage, i oh = C6ma v oh(3.3v) 2.4 C v output high voltage, i oh = C6ma v oh((2.5v)) 1.9 C v output high voltage, i oh = C3ma v oh(1.8v) 1.4 C v output low voltage, i ol = 6ma v ol C 0.4 v capacitance, v in =0 v, f = 1mhz c in C 5.0 pf 2,3 note: 1. for 60x bus signals, the reference is ov dd , while l2ov dd is the reference for the l2 bus signals. 2. jtag port signal levels are controlled by the bvsel pin and are the same as those shown for the 60x bus. lssd_mode, l1_tstclk, and l2tstclk receiver voltage levels are those shown for ovdd = 1.8v nominal, regardless of bvsel. jtag, lssd_mode, l1_tstclk, and l2tstclk values in this table are guaranteed by design and characterization, and are not tested. 3. capacitance values are guaranteed by design and characterization, and are not tested. 4. sysclk input high and low voltage: i/o timings are measured using a rail to rail sysclk; i/o timing may be less favorable if sysclk does not travel from gnd to ov dd. thermal sensor speci?cations see table recommended operating conditions, on page 9, for operating conditions. num characteristic minimum maximum unit notes note: 1. the temperature is the junction temperature of the die. the thermal assist unit's (tau) raw output does not indicate an absol ute temperature, but it must be interpreted by software to derive the absolute junction temperature. for information on how to use and calibrate the ta u, contact ppcsupp@us.ibm.com. this specification reflects the temperature span supported by the design. 2. the comparator settling time value must be converted into the number of cpu clocks that need to be written into the thrm3 spr . for parts with nominal operating frequencies (speed sort) above 266 mhz, the settling time = 20 m s (266/nominal frequency). for example: for 500 mhz parts, settling time = 20 m s (266/500) = 10.6 m s. it is recommended that the maximum value be set in thrm3 under all conditions. 3. this value is guaranteed by design and is not tested. page 12 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 power consumption for 740 and 750 see table recommended operating conditions, on page 9, for operating conditions actual processor cpu frequency unit notes 300 333 350 366 375 400 433 466 500 full-on mode typical 3.7 4.0 4.1 4.3 4.4 4.5 5.0 5.5 6.0 w 1,3,4 maximum 4.5 5.0 5.2 5.5 5.7 6.0 6.3 6.8 7.5 w 1,2,4 doze mode maximum 1.7 1.7 1.7 1.8 1.8 1.9 2.1 2.2 2.3 w 1,2,4 nap mode maximum 250 250 250 250 250 250 250 250 250 mw 1, 4 sleep mode maximum tbd tbd tbd tbd tbd tbd tbd tbd tbd mw 1, 4 note: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically <10% of v dd power. worst case power consumption for av dd = 15mw and l2av dd = 15mw. 2. maximum power is shown for a system executing worst case benchmark sequences at: ?v dd = av dd = l2v dd = 2.1v; ?ov dd = l2ov dd = 3.3v; ?t j = 65 c maximum power at 85 c can be derived by adding 0.1 w to the maximum power shown at 65 c. maximum power at 105 c can be derived by add- ing 0.3 w to the maximum power shown at 65 c. 3. typical power is an average value shown for a system executing typical applications and benchmark sequences at: ?v dd = av dd = l2av dd = 2.0v (300 through 400 mhz); ?v dd = av dd = l2av dd = 2.05v (433 through 500 mhz); ?ov dd = l2ov dd = 3.3v; ?t j = 45 c. 4. guaranteed by design and characterization, and is not tested. 12/8/99 version 1.02 page 13 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 ac electrical characteristics this section provides the ac electrical characteristics for the 750. after fabrication, parts are sorted by maxi- mum processor core frequency as shown in the section clock ac specifications, on page 13, and tested for conformance to the ac specifications for that frequency. parts are sold by maximum processor core fre- quency, subject to the specified application conditions; see section ordering information, on page 46. unless otherwise noted, all timings apply for all i/o supply voltages. clock ac speci?cations the following table provides the clock ac timing specifications as defined in figure 2. clock ac timing speci?cations see table recommended operating conditions, on page 9, for operating conditions. num characteristic fmax = 300-375mhz fmax 3 400mhz unit notes min max min max processor frequency tbd as specified by part number 250 as specified by part number mhz 6 sysclk frequency 25 100 31 100 mhz 1 1 sysclk cycle time 10 40 10 32 ns 2,3 sysclk rise and fall time C 1.0 C 1.0 ns 2,3 4 sysclk duty cycle measured at vm 40 60 40 60 % 3 sysclk jitter C 150 C 150 ps 4,3 internal pll relock time C 100 C 100 m s5 note: 1. caution: the sysclk frequency and the pll_cfg[0:3] settings must be chosen such that the resulting sysclk (bus) frequency, an d cpu (core) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:3] signal description in section pll configuration, on page 36 for valid pll_cfg[0:3] settings. bus operation above 100 mhz is possible, but requires careful timin g analysis. contact ibm for details. 2. rise and fall times for the sysclk input are measured from 0.5 to 1.5v. 3. timing is guaranteed by design and characterization, and is not tested. 4. the total input jitter (short term and long term combined) must be under 150ps. contact ibm for operation with spread spectrum clocks or clocks with more than 150 ps total jitter. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. 6. under certain conditions, operation at core frequencies below those stated is possible. contact ibm for details. figure 2. sysclk input timing diagram vm cv il cv ih 1 2 4 3 4 sysclk vm = ovdd/2 page 14 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 60x bus input ac speci?cations the following table provides the 60x bus input ac timing specifications for the 750 as defined in figure 3 and figure 4. input timing specifications for the l2 bus are provided in section, l2 bus input ac specifications on page 20. 60x bus input timing speci?cations 1 see table recommended operating conditions, on page 9, for operating conditions. num characteristic all frequencies unit notes minimum maximum 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 ns 2 10b all other inputs valid to sysclk (input setup) 2.5 ns 3 10c mode select input setup to hreset (drtry, tlbisync) 8 t sysclk 4,5,6,7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 0.6 ns 2 11b sysclk to all other inputs invalid (input hold) 0.6 ns 3 11c hreset to mode select input hold ( drtry, tlbisync) 0 ns 4,6,7 note: 1. input specifications are measured from the vm of the signal in question to the vm of the rising edge of the input sysclk. input and output timings are measured at the pin (see figure 3 ). 2. address/data transfer attribute inputs are composed of the followingCa[0:31], ap[0:3], tt[0:4], tbst, tsiz[0:2], gbl, dh[0:31], dl[0:31], dp[0:7]. 3. all other signal inputs are composed of the followingC ts, abb, dbb, artry, bg, aack, dbg, dbwo, ta, drtry, tea, dbdis, tben, qack, tlbisync. 4. the setup and hold time is with respect to the rising edge of hreset (see figure 4). 5. t sysclk , is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the pe riod of sysclk to compute the actual time duration (in ns) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll re-lock time during the power-on reset sequence. 12/8/99 version 1.02 page 15 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 figure 3. input timing diagram figure 4. mode select input timing diagram vm sysclk all inputs 10b 10a 11b 11a vm vm vm = 1.4 v for ovdd = 3.3 v., else vm = ovdd/2 v ih v ih = 2.0v mode pins 10c 11c hreset page 16 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 60x bus output ac speci?cations the following table provides the 60x bus output ac timing specifications for the 750 as defined in figure 5. output timing specification for the l2 bus are provided in the section l2 bus output ac specifications, on page 21. 60x bus output ac timing speci?cations for the 750 1 see table recommended operating conditions, on page 9 for operating conditions, c l = 50pf 2 num characteristic all frequencies unit notes minimum maximum 12 sysclk to output driven (output enable time) 0.5 ns 8 13 sysclk to output valid ( ts, abb, artry, dbb, and tbst) C 4.5 ns 5 14 sysclk to all other output valid (all except ts, abb, artry, dbb, and tbst) C 5.0 ns 5 15 sysclk to output invalid (output hold) 1.0 ns 3, 8, 9 16 sysclk to output high impedance (all signals except abb, artry, and dbb) C 6.0 ns 8 17 sysclk to abb and dbb high impedance after precharge C 1.0 t sysclk 4, 6, 8 18 sysclk to artry high impedance before precharge C 5.5 ns 8 19 sysclk to artry precharge enable 0.2 t sysclk + 1.0 ns 3, 4, 7 20 maximum delay to artry precharge 1 t sysclk 4, 7 21 sysclk to artry high impedance after precharge 2 t sysclk 4, 7, 8 note: 1. all output specifications are measured from vm of the rising edge of sysclk to vm of the signal in question. both input and o utput timings are mea- sured at the pin. 2. all maximum timing specifications assume c l = 50pf. 3. this minimum parameter assumes cl = 0pf. 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 5. this footnote has been deleted. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for artry is 1.0 t sysclk . 8. guaranteed by design and characterization, and not tested. 9. connecting l2_tstclk to gnd no longer provides additional output hold. for new designs, l2_tstclk should be pulled up to ovdd , but it can be left connected to gnd in legacy systems. 12/8/99 version 1.02 page 17 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 figure 5. output timing diagram sysclk all outputs (except ts, abb, dbb, ar tr y) ts abb, dbb ar tr y 12 14 13 15 16 16 vm vm 15 vm 13 20 18 17 21 19 vm vm vm vm = 1.4 v for ovdd = 3.3 v., else vm = ovdd/2 page 18 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 l2 clock ac speci?cations the following table provides the l2clk output ac timing specifications for the 750 as defined in figure 6. l2clk output ac timing speci?cations see table recommended operating conditions, on page 9, for operating conditions. num characteristic min max unit notes l2clk frequency 80 250 mhz 1, 5 22 l2clk cycle time 4.0 12.5 ns 23 l2clk duty cycle 50 % 2 internal dll-relock time 640 l2clk 4 l2clk jitter 1 50 ps 3, 6 l2clk skew 0 ps 7 note: 1. l2clk outputs are l2clkouta, l2clkoutb and l2sync_out pins. the internal design supports higher l2clk frequencies. consult ib m pow- erpc application engineering (ppcsupp@us.ibm.com) before operating the l2 srams above 250 mhz. the l2clk frequency to core freq uency set- tings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minim um operating frequencies. l2clkouta and l2clkoutb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measured at midpoint voltage. 3. the major component of l2clk jitter is passed through from sysclk. while sysclk jitter is less then 1 50 ps, l2clk jitter is also less than 1 50 ps. sysclk jitter in excess of 1 50 ps causes l2clk jitter to exceed 1 50 ps. 4. the dll re-lock time is specified in terms of l2clks. the number in the table must be multiplied by the period of l2clk to co mpute the actual time duration in nanoseconds. re-lock timing is guaranteed by design and characterization, and is not tested. 5. the l2cr [l2sl] bit should be set for l2clk frequencies less than 110mhz. 6. guaranteed by design and characterization, not tested. 7. skew between the l2 output clocks is included in the other timing specs. 12/8/99 version 1.02 page 19 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 figure 6. l2clk_out output timing diagram vm 22 l2clk_outa vm vm 23 vm 22 l2clk_outa vm vm 23 l2clk_outb gnd l2ov dd vm l2clk_outb vm vm vm l2sync_out vm vm vm l2sync_out vm vm l2 single-ended clock mode l2 differential clock mode vm = 1.4 v for l2ovdd = 3.3 v., else vm = l2ovdd/2 vm = 1.4 v for l2ovdd = 3.3 v., else vm = l2ovdd/2 page 20 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 l2 bus input ac speci?cations some specifications are shown in the following table as a function of maximum core frequency (fmax). these specifications refer to the effective fmax of the part after derating for application conditions. for exam- ple, a nominal 450 mhz part running at application conditions that derate its fmax to 400 mhz will meet or exceed the specifications shown for fmax = 400 mhz. l2 bus input interface ac timing speci?cations see table recommended operating conditions, on page 9, for operating conditions. num characteristic min max unit notes 29,30 l2sync_in rise and fall time 1.0 ns 2,3 24 data and parity input setup to l2sync_in, fmax up through 375 mhz. 1.5 ns 1 24 data and parity input setup to l2sync_in, fmax = 400 mhz. 1.4 ns 1 24 data and parity input setup to l2sync_in, fmax = 433 and 450 mhz. 1.1 ns 1 24 data and parity input setup to l2sync_in, fmax = 466 and 500 mhz. 1.0 ns 1 25 l2sync_in to data and parity input hold 0.5 ns 1 note: 1. all input specifications are measured from the vm of the signal in question to the vm of the rising edge of the input l2sync_ in. input timings are measured at the pins (see figure 7). 2. rise and fall times for the l2sync_in input are measured from 0.5 to 1.5v. 3. guaranteed by design and characterization, and not tested. figure 7. l2 bus input timing diagrams vm l2sync_in 25 24 all inputs 29 30 vm vm vm = 1.4 v for l2ovdd = 3.3 v., else vm = l2ovdd/2 12/8/99 version 1.02 page 21 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 l2 bus output ac speci?cations l2 bus output interface ac timing speci?cations 1 see table recommended operating conditions, on page 9 for operating conditions, c l = 20pf 3 num characteristic l2cr[14:15] is equivalent to: unit notes 00 2 01 10 11 min max min max min max min max 26 l2sync_in to output valid, fmax 7 up through 375 mhz. 3.2 3.7 rsv 5 rsv 5 ns 26 l2sync_in to output valid, fmax = 400 mhz. 3.0 3.5 rsv 5 rsv 5 ns 26 l2sync_in to output valid, fmax = 433 and 450 mhz. 2.6 3.1 rsv 5 rsv 5 ns 26 l2sync_in to output valid, fmax = 466 and 500 mhz. 2.4 2.9 rsv 5 rsv 5 ns 27 l2sync_in to output hold 0.5 1.0 rsv 5 rsv 5 ns 4,6 28 l2sync_in to high impedance 3.5 4.0 rsv 5 rsv 5 ns 6 note: 1. all outputs are measured from the vm of the rising edge of l2sync_in to the vm of the signal in question. the output timings are measured at the pins (see figure 8). 2. the outputs are valid for both single-ended and differential l2clk modes. for flow-through and pipelined reg-reg synchronous burst srams, l2cr[14:15] = 00 is recommended. for pipelined late-write synchronous burst srams, l2cr[14:15] = 01 is recommended. 3. all maximum timing specifications assume cl = 20pf. 4. this measurement assumes cl= 5pf. 5. reserved for future use. 6. guaranteed by design and characterization, and not tested. 7. specifications are shown as a function of maximum core frequency (fmax). they refer to the effective fmax of the part after d erating for application conditions. for example, a nominal 450 mhz part running at application conditions that derate its fmax to 400 mhz will meet or exceed the specifica- tions shown for fmax = 400 mhz. figure 8. l2 bus output timing diagrams 27 vm l2sync_in 26 all outputs vm 28 l2data bus vm vm vm = 1.4 v for l2ovdd = 3.3 v., else vm = l2ovdd/2 page 22 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 ieee 1149.1 ac timing speci?cations the table below provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 9, figure 10, figure 11, and figure 12. the five jtag signals are; tdi, tdo, tms, tck, and trst. jtag ac timing speci?cations (independent of sysclk) see table recommended operating conditions, on page 9 for operating conditions, c l = 50pf. num characteristic min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.4v 15 ns 3 tck rise and fall times 0 2 ns 4 4 spec obsolete, intentionally omitted 5 trst assert time 25 ns 1 6 boundary-scan input data setup time 4 ns 2 7 boundary-scan input data hold time 16 ns 2 8 tck to output data valid 4 20 ns 3, 5 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 16 ns 12 tck to tdo data valid 2.5 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 note: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum spec guaranteed by characterization and not tested. figure 9. jtag clock input timing diagram 1 2 2 3 3 vm tck vm vm vm = 1.4 v for ovdd = 3.3 v., else vm = ovdd/2 12/8/99 version 1.02 page 23 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 figure 10. trst timing diagram figure 11. boundary-scan timing diagram figure 12. test access port timing diagram 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid 9 13 12 10 11 tck tdi, tms tdo tdo input data valid output data valid page 24 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 powerpc 740 microprocessor pin assignments the following sections contain the pinout diagrams for the powerpc 740, a 255 pin ceramic ball grid array (bga) package. figure 13 (in part a) shows the pinout of the ppc 740, a 255 pin ceramic ball grid array (cbga) package as viewed from the top surface. part b shows the side profile. figure 13. pinout of the powerpc 740 bga package as viewed from the top surface a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale substrate assembly. encapsulation view part b die part a 12/8/99 version 1.02 page 25 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 powerpc 740 microprocessor pinout listings pinout listing for the powerpc 740 255 cbga package signal name pin number active i/o a[0:31] c16, e04, d13, f02, d14, g01, d15, e02, d16, d04, e13, go2, e15, h01, e16, h02, f13, j01, f14, j02, f15, h03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aa ck l02 low input abb k04 low i/o ap[0:3] c01, b04, b03, b02 high i/o ar tr y j04 low i/o avdd a10 bg l01 low input br b06 low output bvsel 1 h04 input ci e01 low output ckstp_in d08 low input ckstp_out a06 low output clk_out d07 output dbb j14 low i/o dbg n01 low input dbdis h15 low input dbw o g04 low input dh[0:31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p09, n09, t10, r09, t09, p08, n08, r08, t08, n07, r07, t07, p06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0:31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p03, n03, n04, r03, t01, t02, p04, t03, r04 high i/o dp[0:7] m02, l03, n02, l04, r01, p02, m04, r02 high i/o dr tr y g16 low input gbl f01 low i/o gnd c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k06, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 page 26 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 hreset a07 low input int b15 low input l1_tstclk 2 d11 high input l2_tstclk 2 d12 high input lssd_mode 2 b10 low input mcp c13 low input nc (no-connect) b07, b08, c03, c06, c08, d05, d06, j16, a04, a05, a02, a03, b01, b05 ovdd c07, e05, e07, e10, e12, g03, g05, g12, g14, k03, k05, k12, k14, m05, m07, m10, m12, p07, p10 pll_cfg[0:3] a08, b09, a09, d09 high input qa ck d03 low input qreq j03 low output rsr v d01 low output smi a16 low input sreset b14 low input sysclk c09 input t a h14 low input tben c02 high input tbst a14 low i/o tck c11 high input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c04 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0:2] a13, d10, b12, high output tt[0:4] b13, a15, b16, c14, c15 high i/o wt d02 low output pinout listing for the powerpc 740 255 cbga package (cont.) signal name pin number active i/o 12/8/99 version 1.02 page 27 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 note: 1. bvsel function if bvsel is connected to gnd with a series resistor, the resistor value must be 10 w or less. 2. these are test signals for factory use only and must be pulled up to ovdd for normal operation. 3. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 4. internally tied to gnd in the 255 cbga package. this is not a supply pin. vdd 3 f06, f08, f09, f11, g07, g10, h06, h08, h09, h11, j06, j08, j09, j11, k07, k10, l06, l08, l09, l11 voltdet 4 f03 low output unconnected or pulled to ovdd (3.3v nominal) ovdd = 3.3 v nominal connected to hreset ovdd = 2.5 v nominal connected to gnd ovdd = 1.8 v nominal pinout listing for the powerpc 740 255 cbga package (cont.) signal name pin number active i/o page 28 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 powerpc 740 package package type ceramic ball grid array (cbga) package outline 21 x 21mm interconnects 255 (16 x 16 ball array - 1) pitch 1.27mm (50mil) minimum module height 2.45mm maximum module height 3.00mm ball diameter 0.89mm (35mil) 12/8/99 version 1.02 page 29 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 mechanical dimensions of the powerpc 740 255 cbga package figure 14. mechanical dimensions and bottom surface nomenclature of the 255 cbga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from dim min max millimeters a 2.45 3.00 a1 0.80 1.00 a2 0.90 1.10 b 0.82 0.93 d 21.00 bsc d1 5.443 bsc e 1.27 bsc e 21.00 bsc e1 8.075 bsc a a1 a2 c 0.15 c b c 255x e 12345678910111213141516 t r p n m l k j h g f e d c b a e/2 a 0.3 c 0.15 b e/2 0.2 d 2x a1 corner e e1 d1 0.2 2x b a there is no ball a1 corner top view x-ray view of balls from top of package in the a01 position page 30 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 powerpc 750 microprocessor pin assignments the following sections contain the pinout diagrams for the powerpc 750 ceramic ball grid array 360 cbga packages. figure 15 (in part a) shows the pinout of the 360 cbga package as viewed from the top surface. part b shows the side profile of the 360 cbga package to indicate the direction of the top surface view. figure 15. pinout of the 750 360 cbga package as viewed from the top surface a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale substrate assembly. encapsulation view part b die part a 17 18 19 u v w 12/8/99 version 1.02 page 31 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 pinout listing for the powerpc 750 360 cbga package signal name pin number active i/o a[0:31] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o aack n3 low input abb l7 low i/o ap[0:3] c4, c5, c6, c7 high i/o artry l6 low i/o avdd 1 a8 bg h1 low input br e7 low output bvsel 2 w01 2 input ckstp_out d7 low output ci c2 low output ckstp_in b8 low input clkout e3 output dbb k5 low i/o dbdis g1 low input dbg k1 low input dbwo d1 low input dh[0:31] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o dl[0:31] m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o dp[0:7] l1, p2, m2, v2, m1, n2, t3, r1 high i/o drtry h6 low input gbl b1 low i/o gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 hreset b6 low input int c11 low input l1_tstclk 3 f8 high input l2addr[0:16] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2avdd l13 l2ce p17 low output l2clkouta n15 output page 32 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 l2clkoutb l16 output l2data[0:63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o l2dp[0:7] v14, u16, t19, n18, h14, f17, c19, b15 high i/o l2ovdd d15, e14, e16, h16, j15, l15, m16, p15, r14, r16, t15, f15 l2sync_in l14 input l2sync_out m14 output l2_tstclk 3 f7 high input l2vsel a19 2 input l2we n16 low output l2zz g17 high output lssd_mode 3 f9 low input mcp b11 low input nc (no-connect) b3, b4, b5, w19, k9, k11 4 , k19 4 ovdd 2 d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 pll_cfg[0:3] a4, a5, a6, a7 high input qack b2 low input qreq j3 low output rsrv d3 low output smi a12 low input sreset e10 low input sysclk h9 input ta f1 low input tben a2 high input tbst a11 low i/o tck b10 high input tdi b7 high input tdo d9 high output tea j1 low input tlbisync a3 low input tms c8 high input trst a10 low input ts k7 low i/o pinout listing for the powerpc 750 360 cbga package (cont.) signal name pin number active i/o 12/8/99 version 1.02 page 33 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 note: 1. for dd3.x on the 750 only, avdd is no longer connected to the bga pin. avdd is ?ltered on the module from vdd. the 740 dd3.2 does require avdd. 2. bvsel and l2vsel function if bvsel or l2vsel is connected to gnd with a series resistor, the resistor value must be 10 w or less. 3. these are test signals for factory use only and must be pulled up to ovdd for normal operation. during normal operation, l2_tstclk can be connected to gnd if required. 4. these pins are reserved for potential future use as additional l2 address pins. 5. ovdd inputs supply power to the i/o drivers, and vdd inputs supply power to the processor core. 6. internally tied to l2ov dd in the 750 360 cbga package. this is not a supply pin. powerpc 750 package package type ceramic ball grid array (cbga) package outline 25 x 25mm interconnects 360 (19 x 19 ball array - 1) pitch 1.27mm (50mil) minimum module height 2.65mm maximum module height 3.20mm ball diameter 0.89mm (35mil) tsiz[0:2] a9, b9, c9 high output tt[0:4] c10, d11, b12, c12, f11 high i/o wt c3 low output vdd 5 g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 voltdet 6 k13 high output unconnected l2ovdd = 3.3 v nominal connected to hreset ovdd = 2.5 v nominal connected to gnd ovdd = 1.8 v nominal pinout listing for the powerpc 750 360 cbga package (cont.) signal name pin number active i/o page 34 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 mechanical dimensions of the powerpc 750 360 cbga package figure 16. mechanical dimensions and bottom surface nomenclature of the 360 cbga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. millimeters dim minimum maximum a 2.65 3.20 a1 0.80 1.00 a2 1.10 1.30 b 0.82 0.93 d 25.00 bsc d1 5.443 d2 2.48 d3 6.3 e 1.27 bsc e 25.00 bsc e1 8.075 e2 2.48 e3 7.43 e 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 u v w a b c d e f g h j k l m n p r t b c 360x a 0.3 c 0.15 b a a1 a2 c 0.15 c not to scale (18x) (18x) 0.2 d 2x e e1 d1 0.2 2x b a a01 corner locator a01 corner chip d2 d3 d2 d3 e3 e2 e3 e2 capacitor note: all caps on the scm are lower in height than the processor die. top view there is no ball in the a01 position a01 corner x-ray view of balls from top of package 12/8/99 version 1.02 page 35 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 notes: 1. for pid8 - 750 dd2.x, this capacitor is connected to vdd. for dd3.x, this capacitor is connected to avdd. 2. for dd3.x, avdd is no longer brought to the bga pin. figure 17. 360 cbga decoupling capacitors l2ovdd l2ovdd vdd gnd gnd gnd gnd gnd gnd ovdd see note 1. vdd vdd ovdd gnd gnd c1 c2 c3 c4 c5 c6 c7 c8 a0 corner chip carrier (pins down) chip 0.83 (typical) 1.85 (typical) 0.51 (typical) 3.45 typical page 36 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 system design information pll con?guration the 750 pll is configured by the pll_cfg[0:3] signals. for a given sysclk (bus) frequency, the pll con- figuration signals set the internal cpu and vco frequency of operation. pll con?guration pll_cfg (0:3) processor to bus frequency ratio vco divider 5 bin dec 0000 0 rsv 1 n/a 0001 1 7.5x 2 0010 2 7x 2 0011 3 pll bypass 3 n/a 0100 4 2x 6 2 0101 5 6.5x 2 0110 6 10x 2 0111 7 4.5x 2 1000 8 3x 2 1001 9 5.5x 2 1010 10 4x 2 1011 11 5x 2 1100 12 8x 2 1101 13 6x 2 1110 14 3.5x 2 1111 15 off 4 n/a note: 1. reserved settings. 2. sysclk min is limited by the lowest frequency that manufacturing will support, see section , clock ac specifications, for v alid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing specifications given in the document do not apply in pll-bypass mode. 4. in clock-off mode, no clocking occurs inside the 750 regardless of the sysclk input. 5. the vco to core clock ratio is 2x for 740/750. this simplifies clock frequency calculations so the user can disregard the vco frequency. the vco will operate correctly when the core clock is within specification. 6. not tested. 12/8/99 version 1.02 page 37 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 pll power supply filtering the av dd and l2avdd are power signals provided on the 750 to provide power to the clock generation phase- locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 18. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. for dd3.2, avdd is filtered on the module from vdd for the 750 only and can be connected or not, at the designers convenience. the 740 requires avdd to be supplied as usual. decoupling recommendations due to the dynamic power management of the 750, which features large address and data buses, as well as high operating frequencies, the 750 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 750 system, and the 750 itself requires a clean, tightly regulated source of power. therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low esr (effective series resistance) rating at each v dd and ov dd pin (and l2ov dd for the 360 cbga) of the 750. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should range in value from 220pf to 10 m f to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated v dd or ov dd pins. suggested values for the v dd pins C 220pf (ceramic), 0.01 m f (ceramic), and 0.1 m f (ceramic). suggested values for the ov dd pins C 0.01 m f (ceramic), 0.1 m f (ceramic), and 10 m f (tantalum). only smt (surface-mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feed- ing the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors C 100 m f (avx tps tantalum) or 330 m f (avx tps tantalum). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to v dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd, pins of the 750. figure 18. pll power supply filter circuit vdd av dd (or l2av dd ) 10 w 10 m f 0.1 m f gnd page 38 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 external clock routing should ensure that the rising edge of the l2 clock is coincident at the clk input of all srams and at the l2sync_in input of the 750. the l2clkouta network could be used only, or the l2clkoutb network could also be used depending on the loading, frequency, and number of srams. output buffer dc impedance the 750 60x and l2 i/o drivers were characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or gnd. then the value of such resistor is varied until the pad voltage is ov dd /2; see figure 19, driver impedance measurement, below. the output impedance is actually the average of two components, the resistances of the pull-up and pull- down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad = ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value, then z 0 = (r p + r n )/2. the following table summarizes the impedance a board designer would design to for a typical process. these values were derived by simulation at 65 c. as the process improves, the output impedance will be lower by several ohms than this typical value. figure 19. driver impedance measurement impedance characteristics v dd = 1.9v dc , l2ov dd =ov dd = 3.3v dc , t j = 65 c process 60x l2 symbol unit typical 43 38 z 0 w data ov dd r n sw2 sw1 pad r p gnd 12/8/99 version 1.02 page 39 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 pull-up resistor requirements the 750 requires high-resistive (weak: 10k w ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 750 or other bus masters. these signals are: ts, abb, dbb, tbst, gbl, and artry. in addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7k w - 1k w ) if it is used by the system. this signal is: ckstp_out. if address or data parity is not used by the system, it should be disabled using hid0. this also disables the parity input receivers. in most systems, the unused (and disabled) parity pins can be left unconnected; how- ever, in some systems, these parity pins must be pulled up to ovdd by a weak (or stronger) pull-up. no pull-up resistors are normally required for the l2 interface, the 60x bus address and ap lines, or the 60x bus data and dp lines. the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. hreset and gbl must be actively driven. resistor pull-up / pull-down requirements required or recommended actions signals strong pull-up required ckstp_out weak pull-up required tlbisync, lssd_mode, l1_tstclk, l2tstclk, ts, abb, dbb, artry, gbl, tbst weak pull-up or pull-down required tck weak pull-up recommended sreset, smi, int, mcp, ckstp_in weak pull-up recommended if pin not used ap[0:3], dp[0:3] errata summary # problem description impact solution(s) applies to version 3.2 1 l2 cache invalidate may fail with dpm enabled. if dpm is enabled during a global invalidate of the l2 cache, the global invalidate may not invali- date all the l2s tags. possible system failure after l2 initialization and start-up. turn dpm off during a l2 tag invalidate. yes 3 dcbz that hits in l1 cache may not retry snoop. if a dcbz hits in the l1 cache, a snoop received at the same time to that address may not be ser- viced or get retried. stale data from system memory may be read by the other bus master, and the line may become valid in multiple caches. limit use of dcbz to data that is protected through software syn- chronization. yes 5 segment register updates may corrupt data translation. mtsr page 40 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 thermal management information this section provides thermal management information for the cbga package for air cooled applications. proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air flow, and the thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly, see figure 20. figure 20. package exploded cross-sectional view with several heat sink options maximum heatsink weight limit for the 360 cbga force maximum (pounds) dynamic compression 10.0 dynamic tensile 2.5 static constant (spring force) 8.2 cbga package heat sink heat sink clip adhesive or thermal interface material printed option circuit board 12/8/99 version 1.02 page 41 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 the board designer can choose between several types of heat sinks to place on the 750. there are several commercially-available heat sinks for the 750 provided by the following vendors: chip coolers, inc. 800-227-0254 (usa/canada) 333 strawberry field rd. 401-739-7600 warwick, ri 02887-6979 thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 aavid engineering 603-528-3400 one kool path laconic, nh 03247-0440 wakefield engineering 617-245-5900 60 audubon rd. wakefield, ma 01880 ultimately, the final selection of an appropriate heat sink for the 750 depends on many factors, such as ther- mal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. internal package conduction resistance for the exposed-die packaging technology, shown in table package thermal characteristics1, on page 10, the intrinsic conduction thermal resistance paths are as follows. ? die junction-to-case thermal resistance ? die junction-to-ball thermal resistance figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. page 42 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink; where it is removed by forced- air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/con- vective thermal resistances are the dominant terms. adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by a spring clip mechanism, figure 22 shows the thermal performance of three thin-sheet thermal-interface materials (silicon, graphite/oil, flouroether oil), a bare joint, and a joint with thermal grease, as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of ther- mal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 20). therefore the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors C thermal per- formance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 21. c4 package with heat sink mounted to a printed-circuit board external resistance external resistance internal resistance (note the internal versus external package resistance.) radiation convection radiation convection heat sink die/package printed-circuit board thermal interface material package/leads chip junction 12/8/99 version 1.02 page 43 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 the board designer can choose between several types of thermal interfaces. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors. dow-corning corporation 517-496-4000 dow-corning electronic materials p.o. box 0997 midland, mi 48686-0997 figure 22. thermal performance of select thermal interface material speci?c thermal resistance (kin 2 /w) 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 contact pressure (psi) + + + silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease + page 44 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 thermagon, inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g. eg7655) 609-882-2332 1425 lower ferry road trent, nj 08618 the following section provides a heat sink selection example using one of the commercially available heat sinks. heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows. t j = t a + t r + ( q jc + q int + q sa ) p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the system cabinet q jc is the junction-to-case thermal resistance q int is the thermal resistance of the thermal interface material q sa is the heat sink-to-ambient thermal resistance p d is the power dissipated by the device typical die-junction temperatures (t j ) should be maintained less than the value specified in table package thermal characteristics1, on page 10. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the interface material ( q int ) is typically about 1 c/ w. assuming a t a of 30 c, a t r of 5 c, a cbga package q jc = 0.03, and a power dissipation (p d ) of 5.0 watts, the following expression for t j is obtained. die-junction temperature: t j = 30 c + 5 c + (0.03 c/w +1.0 c/w + q sa ) 5w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( q sa ) versus air flow velocity is shown in figure 23. 12/8/99 version 1.02 page 45 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 assuming an air velocity of 0.5m/s, we have an effective q sa of 7 c/w, thus t j = 30 c + 5 c + (.03 c /w +1.0 c /w + 7 c /w) 4.5w, resulting in a junction temperature of approximately 71 c which is well within the maximum operating temper- ature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, aavid, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of- merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final chip-junction operating tempera- ture is not only a function of the component-level thermal resistance, but the system-level design and its oper- ating conditions. in addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. these factors might include air flow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air temperature rise, etc. figure 23. thermalloy #2328b pin-fin heat sink-to-ambient thermal resistance vs. air ?ow velocity approach air velocity (m/s) heat sink thermal resistance ( c/w) 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-?n heat sink (25 x 28 x 15 mm) page 46 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 ordering information this section provides the part numbering nomenclature for the 750. note that the individual part numbers cor- respond to a maximum processor core frequency. for available devices contact your local ibm sales office. figure 24. part number key the cmos 0.20 m m ibm25ppc750l-gbyyya2t package (cbga) revision levels: e= 2.2 processor frequency application conditions: a = 2.0 - 2.2v, -40 - 65 c revision level letter g rev dd 3.2 processor version register 0008 8302 revision levels: g=3.2 reliability grade (2=25 fit) shipping container t=tray r=tape and reel copper technology, pid-8p, implementation of the powerpc 740 and powerpc 750 page 47 version 1.02 12/8/99 powerpc 740 and powerpc 750 microprocessor cmos 0.20 m m copper technology, pid-8p, ppc740l and ppc750l, dd3.2 ? international business machines corporation 1999 printed in the united states of america 12/99 all rights reserved the information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibms product speci?cations or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in speci?c environments, and is presented as illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an as is basis. in no event will ibm be lia- ble for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com |
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